Many semiconductor processing foundries have a maximum lithographic size they may use to form a chip. A common limit, for example, is 20xc3x9720 mm2. Making a chip larger than that maximum size may be carried out using stitching. Stitching forms different portions of the chip in different areas of the wafer. The different areas are then xe2x80x9cstitchedxe2x80x9d together with interconnect lines to form the overall chip.
Complicated chips may require a large number of stitches to form an entire circuit. The complexity of the chips may increase the cost and defect rate of the chips and lower throughput in the chip production process.
A binary decoder block according to an embodiment includes a number N of generic blocks which are stitched together. Each generic decoder block includes a number of address lines for addressing decoders in the generic decoder block, and no more than 2*(2kxe2x88x921)+N block address lines for addressing the generic blocks, where k is the whole number portion of log2(Nxe2x88x921).
A gray decoder block according to an embodiment includes a number N of generic blocks which are stitched together. Each generic decoder block includes a number of address lines for addressing decoders in the generic decoder block, and no more than 2*(2kxe2x88x921)+2(Nxe2x88x921) block address lines for addressing the generic blocks.
A decoder block according to an alternate embodiment includes a number N of generic blocks which are stitched together. Each generic decoder block includes a number of address lines for addressing decoders in the generic decoder block, and no more than N block address lines. The decoder block includes a block address decoder for selecting block address lines corresponding to a selected generic block in the decoder block.
In a sensor including the decoder block and a pixel section, the features in the decoder block may have a smaller pitch than the features in the pixel section, for example, a ratio of 0.98 or less. The smaller pitch of the decoder block may provide more area on the silicon surface of the chip for the routing liens used to stitch together the component blocks of the decoder block. Interconnects between the decoder block and the pixel section may be angled to accommodate the larger stitching sections.